1. Field of the Invention
The present invention relates in general to a process for fabricating dual-gate CMOS for a semiconductor device. In particular, the present invention relates to a process for fabricating in-situ nitrogen-doped polysilicon for dual-gate CMOS utilizing the method of rapid thermal chemical vapor deposition.
2. Technical Background
The dual-gate CMOS structure using the p.sup.+ polysilicon for PMOSFET has been widely studied to improve its short-channel behavior. Unfortunately, boron penetration from heavily-doped p.sup.+ polysilicon causes deterioration of the gate oxide and unstable threshold voltage. Several structures have been proposed to avoid boron penetration. For example, in an article "A P.sup.+ Poly-Si Gate with Nitrogen-Doped Poly-Si Layer for Deep Submicron PMOSFETs," ECS Spring Meeting Proc., p. 9, 1991, S. Nakayama disclosed a new p.sup.+ polysilicon gate with a very thin nitrogen-doped polysilicon layer at the polysilicon gate/SiO.sub.2 interface for deep submicron PMOSFETs. Likewise, F. A. Baker et al. in their article in Tech. Dig. of IEDM, p. 443, 1989, as well as T. Kuroi et al. in their article in Tech. Dig. of IEDM, p. 325, 1993, all addressed the same problems of the conventional dual-gate CMOS as indicated above.
However, no prior art process has been capable of fabricating a dual-gate CMOS having its gate configuration through an in-situ process without atmospheric exposure in a single load-locked rapid thermal reactor, that achieves good device electrical characteristics. A dual-gate CMOS may only be considered to feature good electrical behavior if it presents good suppression of boron penetration, smaller flatband voltage shift, improved charge trapping and reliability characteristics.